DFT

We have expert management to oversee project progress, methodology, checklists and regular reviews to ensure predictable results and schedule. We offer complete physical implementation services which includes Synthesis, DFT, Floor planning, IO placement, block placement, Power planning, CTS, Place & Route, Physical verification ATPG and STA signoff.

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Our services include

  • IP/Block Hardening:

    Expertise in mixed signal and digital IP hardening. Work experience on high speed interface IPs such as DDR, Serdes

  • Full Chip or Block Level Implementation:

    Expertise in end to end flow from RTL/netlist to GDSII. Design planning, full chip level floorplan, bump planning, RDL implementation, timing budgeting, power planning, PnR

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  • ECO’s:

    Expertise in functional and timing ECO’s. Work experience on implementing complex ECOs, manual and automated methods, quick convergence to sign off quality

  • DFT:

    Scan Insertion, MBIST, Boundary Scan& ATPG

Expertise

  • Technology nodes

    Worked on all latest nodes 14nm, 10nm and 7nm.

  • Design Complexity

    1.5 million gates to 10million gates with multiple clock domains and power domains

  • Fab Houses

    Team has experience in working with all leading fab houses.

  • Tools

    Worked with all popular industry standard tool flows like Synopsys, Cadence, Magma, Mentor, Apache.

  • Low Power

    Multi power domains upto 6 domains, expertise in designing power intent, low power checks, design sanity