Cerium Systems emerged as a world class expertise to provide best chip design solution for its customers with its focused and efficient specialized team in backend physical design with a legacy of 40+ tape-outs in technology nodes varying from180 nm to 10nm.
Our well-trained engineers in backend design are expertise with all the popular industry standard tool flows and have experience working with leading fab houses.
We excel at delivering perfect product designs at fast turnaround with our well-defined and customizable execution and sign-off processes.
Our services include
Expertise in mixed signal and digital IP hardening. Work experience on high speed interface IPs such as DDR, Serdes
Full Chip or Block Level Implementation:
Expertise in end to end flow from RTL/netlist to GDSII. Design planning, full chip level floorplan, bump planning, RDL implementation, timing budgeting, power planning, PnR
Expertise in functional and timing ECO’s. Work experience on implementing complex ECOs, manual and automated methods, quick convergence to sign off quality
Scan Insertion, MBIST, Boundary Scan& ATPG
Worked on all latest nodes 14nm, 10nm and 7nm.
1.5 million gates to 10million gates with multiple clock domains and power domains
Team has experience in working with all leading fab houses.
Worked with all popular industry standard tool flows like Synopsys, Cadence, Magma, Mentor, Apache.
Multi power domains upto 6 domains, expertise in designing power intent, low power checks, design sanity