Verification is one of the key issues in IC design and development impacting product schedules and timelines. Cerium offers a wide range of ASIC verification services to help customers achieve working silicon the first time.
Rapid progresses in silicon technology offer excellent possibilities in including digital / analog cells, embedded processors, high speed IO, memories, in-house / 3rd-party IP and more onto a single device. Existing verification techniques are inadequate in handling these complexities. Our verification resources understand the challenges involved in such designs and work closely with customers to offer specific solutions that help in achieving the required capability on a complete chip.
Our services include
Full chip verification:
Proficiency in building SoC verification environment from scratch as well as legacy environment.
Module / IP Verification:
Module level verification experience in wide variety of domains - Networking, Image / Video processing, x86 Processors, Bus protocols
VIP development expertise from scratch in various domains.
Gate Level Simulation:
Full chip gate level simulations
Low Power Verification:
Expertise in low power verification methodology with CPF, UPF
Assertion Based Verification:
Assertion based verification for successful and faster closure of designs using SVA & PSL
Multi Language Expertise:
Expertise in System Verilog, Vera, Specman E, C, C++, Verilog
Adaption of industry standard methodology for new environments using UVM/OVM/VMM. Upgrading of legacy environment to comply to UVM
Functional coverage implementation, analysis and closure. RTL Code coverage
The automation and scripting experience goes in Perl, Python, Ruby, Tcl and Shell
Directed and Constrained Random Verification
ASIC emulation and prototyping is an essential tool to verify the functionality. We provide you with unbiased technology and system architecture advice that perfectly matches your project requirements, budget and schedule.
RTL Quality Check
Our team of experienced design engineers, complemented by a group of mid-level engineers have worked on multiple aspects of the RTL design flow on chips used in the automotive, mobile, networking, multimedia and processor industries.