ASIC Design

Over the past few years, the consumer revolution has led to a convergence of applications on a single device. This convergence has resulted in increasing demands on design complexity and design performances like as higher speed, tighter control, and increased product differentiation. The increasing complexity, interface, and functionality of SoCs have brought out much more challenges than the traditional chip implementation.

The growing number and complexity of IP blocks and subsystems in today's SoC designs challenge even the most experienced design teams, especially when the IP is based on a protocol that is new or otherwise unfamiliar to the team.

Cerium System supports SOC design from Architecture specifications to tape out. We have experienced team those are responsible for design challenges and performance estimates, SoC configuration and integration at lower development costs and meet the stringent time-to-market requirements in today’s competitive global economy. We focus on optimizing various parameters to achieve the right PPA - Power, Performance, and Area, specific to your device and its requirements.

Our team has experience in providing solutions for various sectors like automobile, networking, mobile, IOT, microprocessors, multimedia and cloud computing.


Our services include

  • IP Design

    Expertise in developing IP’s from scratch. Cerium has extensive experience in developing IP’s for high-speed interfaces, memory controllers, video codes, networking etc.

  • SOC/Sub-system Integration:

    Expertise in integration, front-end tool flow setup and analysis.

  • Test chip Dev

    Expertise in end to end test chip development for mixed signal IP’s.

  • IP Maintenance& support

    Expertise in maintaining legacy IPs for adding new features, post-silicon bug fixes, making process changes and supporting SOC teams.


  • Mixed Signal IPs

    Extensively worked on mixed signal IPs like PCIe, LPDDR, DDR, USB, MIPI etc.

  • High Speed Interfaces

    JESD204B, JESD204C, Ethernet, Memory controllers etc.

  • Bus Protocols

    APB, AHB, AXI and various custom bus fabrics.

  • Tool flows

    Worked with all popular front-end tools for Lint, CDC, Low Power and Synthesis from Synopsys, Cadence, Mentor etc.